High performance ADCs do not typically follow the “Moore's Law” area and power curves achieved by digital circuits in scaling CMOS process technology. The noise and resolution specifications of an ADC dictate power constraints (lower noise requires higher power) and area limits (to exceed component matching requirements). In addition, as the sampling rates of ADCs increase, typical architectures fail to deliver the required performance due to timing limitations.
Referring to FIG. 1A of the drawings, reference numeral 100 generally designates a conventional ADC 100. ADC 100 generally comprises several stages 102-1 to 102-N, an ADC 106 (which is typically a flash ADC), and a digital output circuit 104. The stages 102-1 to 102-N are generally coupled in series with one another in a sequence, where the first stage 102-1 receives the analog input signal and where each of the subsequent stages 102-2 to 102-N receives a residue signal from the previous stage 102-1 to 102-(N−1), respectively. ADC 106 is coupled to the last stage 102-N (receiving its residue signal). Based on its input signal (either a residue signal or the analog input signal), stages 102-1 to 102-N and ADC 106 are able to resolve a portion of the analog input signal, which is provided to digital output circuit 104. Digital output circuit 104 can then perform error correction or other digital processing to generate the digital output signal DOUT.
Turning now to FIGS. 1B and 1C, stages 102-1 to 102-N can be seen in greater detail (which are referred to hereinafter as stage 102 for the sake of simplicity). Stage 102 generally comprises a track-and-hold (T/H) circuit 108 (i.e., T/H amplifier), ADC 110, digital-to-analog converter (DAC) 112, adder 114, and a residue amplifier 116. In operation, the T/H circuit 110 enters a track phase T during the logic high state of the clock signal CLK and a hold phase H during the logic low state of the clock signal CLK. During the track phase T, the T/H circuit samples its analog input signal SIN (which may be the analog input signal AIN or the residue signal from the previous stage). During the hold phase H, the sampled signal is provided to ADC 110 and adder 114. The ADC 110 resolves a portion of the signal SIN, providing the resolved bits to digital output circuit 104 and DAC 112. DAC 112 converts the resolved bits to an analog signal which is provided to adder 114. Adder 114 determines the difference between the sampled signal and the analog signal from DAC, which is amplified by amplifier 116 and output as a residue signal ROUT.
There are some drawbacks to ADC 100. In particular, timing can disadvantage the performance. In operation, analog processing (quantization by ADC 110 and DAC 112, subtraction by adder 114, and amplification by amplifier 116) occurs within a very tight time, namely within one-half of the period of the clock signal CLK (which operates as a sampling clock). While ADC 100 is well-suited for low noise systems, it is generally limited to low sampling rates to allow for sufficient time for analog processing.
Turning to FIGS. 2A through 2C, another example of a conventional ADC 200 can be seen. ADC 200 has the same general functionality as ADC 100. However, a difference exists in the pipeline; namely, stages 102-1 to 102-N have been replaced by stages 202-1 to 202-N and input amplifier 204. A difference between stage 102 (of FIG. 1B) and stage 202-1 to 202-N (hereinafter 202) is that an additional T/H circuit 206 is interposed between T/H circuit 108 and adder 114. T/H circuits 108 and 206 enter track phases T and hold phases H in opposite logic states of clock signal CLK. This arrangement allow for relaxed timing because a sampled signal is held for an entire period of the clock signal CLK, but the addition of T/H circuit 206 adds noise (i.e., about 3 dB per T/H circuit 206). To compensate for noise degradation, the power consumption for each T/H circuit 108 and 206 is doubled, resulting in four times the power consumption of the single T/H system.
Therefore, there is a need for an improved ADC.
Some examples of other conventional circuits are: U.S. Pat. No. 3,059,228; U.S. Pat. No. 3,735,392; U.S. Pat. No. 3,820,112; U.S. Pat. No. 5,180,932; and U.S. Pat. No. 5,391,936.